The semiconductor industry continually shrinks device dimensions to create faster devices. One such feature that is decreased is the width of polysilicon lines, which form the gate electrode of transistors. Metal silicide, formed on narrow polysilicon lines, improves contact resistance between the polysilicon line and other subsequently formed conductive lines. The metal silicide is formed by depositing a metal layer on the narrow polysilicon line and annealing the metal layer so that it reacts with the polysilicon line and forms a metal silicide. However, when forming a metal silicide over a narrow polysilicon line, it is difficult to nucleate the metal silicide. Poor nucleation results in large variations of thickness and often in noncontinuous layers, which undesirably increase the line sheet resistance of the layer. Due to the increase in line sheet resistance, devices being formed fail and yield decreases. Therefore, a need exists to form metal silicide over narrow polysilicon lines without decreasing yield.